| Inputs: | |
| Poll | Enables reset input and tri-state outputs |
| DI[0..15] | 16 pixel inputs |
| Cal Pulser | Variable amplitude square pulse from I/O gate array |
| Reset | Clears FEA after data is processed |
| CPUWR* | 8086 write strobe |
| AD[0..4] | Buffered and gated 8086 address/data bus, AD[1..5] |
| ALE | 8086 Address latch enable |
| EN* | Chip enable |
| EnGate | Enables CPUWR*, ALE, and AD[0..4] into the FEA |
| Outputs: | |
| Energy | Analog energy to PHA and DPU |
| Pixel[0..3] | Pixel ID |
| Event Window | Coincidence window |
| Event Anti | Anti flag to FPGA |
|
|