PHA/Scaler Gate Array Features

16-channel stacked discriminator (log/linear) with programmable endpoints set by two 8-bit DACs.

Eight 16-bit scalers with overflow bits and buffers.

16-bit computer bus interface.

Set-up latches (24 bits).

State logic directs the collection and storage of spectra in a dedicated 8K x 8 RAM.

The RAM is organized as 4K 16-bit words.

Data router and increments logic accumulate up to 256 160-channel spectra.

Control logic to multiplex four front-end chips and isolate them from the computer bus.

3-to-8 decoder with five external outputs.